Chips and modules
Standard name Memory clock
(MHz) Cycle time4
(ns) I/O bus clock
(MHz) Data rate
(MT/s) VDDQ
(V) Module name Peak alteration rate
(MB/s) Timings
(CL-tRCD-tRP)
DDR-200 100 10 100 200 2.5±0.2 PC-1600 1600
DDR-266 133⅓ 7.5 133⅓ 266⅔ PC-2100 2133⅓
DDR-333 166⅔ 6 166⅔ 333⅓ PC-2700 2666⅔
DDR-400A
DDR-400B
DDR-400C 200 5 200 400 2.6±0.1 PC-3200 3200 2.5-3-3
3-3-3
3-4-4
Note: All aloft listed are defined by JEDEC as JESD79F.5 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application tighter-tolerance or overvolted chips.
The amalgamation sizes in which DDR SDRAM is bogus are aswell connected by JEDEC.
There is no architectural aberration amid DDR SDRAM advised for altered alarm frequencies, for example, PC-1600, advised to run at 100 MHz, and PC-2100, advised to run at 133 MHz. The amount artlessly designates the abstracts amount at which the dent is affirmed to perform, appropriately DDR SDRAM is affirmed to run at lower (underclocking) and can possibly run at college (overclocking) alarm ante than those for which it was made.6
DDR SDRAM modules for desktop computers, frequently alleged DIMMs, accept 184 pins (as against to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the amount of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for anthology computers, SO-DIMMs, accept 200 pins, which is the aforementioned amount of pins as DDR2 SO-DIMMs. These two blueprint are alveolate actual analogously and affliction accept to be taken during admittance if borderline of a actual match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can decidedly abate ability consumption. Chips and modules with DDR-400/PC-3200 accepted accept a nominal voltage of 2.6 V.
Increasing operating voltage hardly can access best speed, at the amount of college ability amusement and heating, and at the accident of adulterated or damage.
Many new chipsets use these anamnesis types in multi-channel configurations.
Standard name Memory clock
(MHz) Cycle time4
(ns) I/O bus clock
(MHz) Data rate
(MT/s) VDDQ
(V) Module name Peak alteration rate
(MB/s) Timings
(CL-tRCD-tRP)
DDR-200 100 10 100 200 2.5±0.2 PC-1600 1600
DDR-266 133⅓ 7.5 133⅓ 266⅔ PC-2100 2133⅓
DDR-333 166⅔ 6 166⅔ 333⅓ PC-2700 2666⅔
DDR-400A
DDR-400B
DDR-400C 200 5 200 400 2.6±0.1 PC-3200 3200 2.5-3-3
3-3-3
3-4-4
Note: All aloft listed are defined by JEDEC as JESD79F.5 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application tighter-tolerance or overvolted chips.
The amalgamation sizes in which DDR SDRAM is bogus are aswell connected by JEDEC.
There is no architectural aberration amid DDR SDRAM advised for altered alarm frequencies, for example, PC-1600, advised to run at 100 MHz, and PC-2100, advised to run at 133 MHz. The amount artlessly designates the abstracts amount at which the dent is affirmed to perform, appropriately DDR SDRAM is affirmed to run at lower (underclocking) and can possibly run at college (overclocking) alarm ante than those for which it was made.6
DDR SDRAM modules for desktop computers, frequently alleged DIMMs, accept 184 pins (as against to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the amount of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for anthology computers, SO-DIMMs, accept 200 pins, which is the aforementioned amount of pins as DDR2 SO-DIMMs. These two blueprint are alveolate actual analogously and affliction accept to be taken during admittance if borderline of a actual match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can decidedly abate ability consumption. Chips and modules with DDR-400/PC-3200 accepted accept a nominal voltage of 2.6 V.
Increasing operating voltage hardly can access best speed, at the amount of college ability amusement and heating, and at the accident of adulterated or damage.
Many new chipsets use these anamnesis types in multi-channel configurations.
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