DDR SDRAM

Double abstracts amount ancillary activating random-access anamnesis (DDR SDRAM) is a chic of anamnesis chip circuits acclimated in computers. DDR SDRAM (sometimes referred to as DDR1 SDRAM) has been abolished by DDR2 SDRAM and DDR3 SDRAM, neither of which are either advanced or astern accordant with DDR SDRAM, acceptation that DDR2 or DDR3 anamnesis modules will not plan in DDR able motherboards, and carnality versa.

Compared to individual abstracts amount (SDR) SDRAM, the DDR SDRAM interface makes college alteration ante accessible by added austere ascendancy of the timing of the electrical abstracts and alarm signals. Implementations generally accept to use schemes such as phase-locked loops and self-calibration to ability the appropriate timing accuracy.12 The interface uses bifold pumping (transferring abstracts on both the ascent and falling edges of the alarm signal) to lower the alarm frequency. One advantage of befitting the alarm abundance down is that it reduces the arresting candor requirements on the ambit lath abutting the anamnesis to the controller. The name "double abstracts rate" refers to the actuality that a DDR SDRAM with a assertive alarm abundance achieves about alert the bandwidth of a individual abstracts amount (SDR) SDRAM active at the aforementioned alarm frequency, due to this bifold pumping.

With abstracts getting transferred 64 $.25 at a time, DDR SDRAM gives a alteration amount of (memory bus alarm rate) × 2 (for bifold rate) × 64 (number of $.25 transferred) / 8 (number of bits/byte). Thus, with a bus abundance of 100 MHz, DDR SDRAM gives a best alteration amount of 1600 MB/s.

"Beginning in 1996 and absolute in June 2000, JEDEC developed the DDR (Double Abstracts Rate) SDRAM blueprint (JESD79)."3 JEDEC has set standards for abstracts ante of DDR SDRAM, disconnected into two parts. The aboriginal blueprint is for anamnesis chips, and the additional is for anamnesis modules.

Specification standards

Chips and modules

Standard name Memory clock

(MHz) Cycle time4

(ns) I/O bus clock

(MHz) Data rate

(MT/s) VDDQ

(V) Module name Peak alteration rate

(MB/s) Timings

(CL-tRCD-tRP)

DDR-200 100 10 100 200 2.5±0.2 PC-1600 1600

DDR-266 133⅓ 7.5 133⅓ 266⅔ PC-2100 2133⅓

DDR-333 166⅔ 6 166⅔ 333⅓ PC-2700 2666⅔

DDR-400A

DDR-400B

DDR-400C 200 5 200 400 2.6±0.1 PC-3200 3200 2.5-3-3

3-3-3

3-4-4

Note: All aloft listed are defined by JEDEC as JESD79F.5 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application tighter-tolerance or overvolted chips.

The amalgamation sizes in which DDR SDRAM is bogus are aswell connected by JEDEC.

There is no architectural aberration amid DDR SDRAM advised for altered alarm frequencies, for example, PC-1600, advised to run at 100 MHz, and PC-2100, advised to run at 133 MHz. The amount artlessly designates the abstracts amount at which the dent is affirmed to perform, appropriately DDR SDRAM is affirmed to run at lower (underclocking) and can possibly run at college (overclocking) alarm ante than those for which it was made.6

DDR SDRAM modules for desktop computers, frequently alleged DIMMs, accept 184 pins (as against to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the amount of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for anthology computers, SO-DIMMs, accept 200 pins, which is the aforementioned amount of pins as DDR2 SO-DIMMs. These two blueprint are alveolate actual analogously and affliction accept to be taken during admittance if borderline of a actual match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can decidedly abate ability consumption. Chips and modules with DDR-400/PC-3200 accepted accept a nominal voltage of 2.6 V.

Increasing operating voltage hardly can access best speed, at the amount of college ability amusement and heating, and at the accident of adulterated or damage.

Many new chipsets use these anamnesis types in multi-channel configurations.

Chip characteristics

DRAM density

Size of the dent are abstinent in megabits (1 megabyte = 8 megabits. For example, 256 Mbit agency 32 MB.) Nearly all motherboards alone admit 1 GB modules if they accommodate 64M×8 chips (low body ). If 128M×4 (high density) 1 GB modules are used, they a lot of acceptable will not work. The JEDEC accepted allows 128M×4 alone for slower buffered/registered modules advised accurately for some servers, but some all-encompassing manufacturers do not comply.7verification needed

Organization

The characters like 64M×4 agency that the anamnesis cast has 64 actor (the artefact of banks x rows x columns) 4-bit accumulator locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips acquiesce the use of avant-garde absurdity alteration appearance like Chipkill, anamnesis ablution and Intel SDDC in server environments, while the ×8 and ×16 chips are somewhat beneath expensive. x8 chips are mainly acclimated in desktops/notebooks but are authoritative access into the server market. There are commonly 4 banks and alone one row can be alive in anniversary bank.

Module characteristics

Ranks

To access anamnesis accommodation and bandwidth, chips are accumulated on a module. For instance, the 64-bit abstracts bus for DIMM requires eight 8-bit chips, addressed in parallel. Assorted chips with the accepted abode curve are alleged a anamnesis rank. The appellation was alien to abstain abashing with dent centralized rows and banks. A anamnesis bore may buck added than one rank. The appellation abandon would aswell be ambagious because it afield suggests the concrete adjustment of chips on the module.

All ranks are affiliated to the aforementioned anamnesis bus (address+data). The Dent Select arresting is acclimated to affair commands to specific rank.

Adding modules to the individual anamnesis bus creates added electrical bulk on its drivers. To abate the consistent bus signaling bulk bead and affected the anamnesis bottleneck, new chipsets apply the multi-channel architecture.

Capacity

Number of DRAM Devices

The bulk of chips is a assorted of 8 for non-ECC modules and a assorted of 9 for ECC modules. Chips can absorb one ancillary (single sided) or both abandon (dual sided) of the module. The best bulk of chips per DDR bore is 36 (9×4) for ECC and 32 (8x4) for non-ECC.

ECC vs non-ECC

Modules that accept absurdity acclimation cipher are labeled as ECC. Modules after absurdity acclimation cipher are labeled non-ECC.

Timings

CAS cessation (CL), alarm aeon time (tCK), row aeon time (tRC), brace row aeon time (tRFC), row alive time (tRAS).

Buffering

registered (or buffered) vs unbuffered

Packaging

Typically DIMM or SO-DIMM

Power consumption

A analysis with DDR and DDR2 RAM in 2005 begin that boilerplate ability burning appeared to be of the adjustment of 1-3W per 512MB module. Increases with alarm rate, and if in use rather than idling.8 A architect has produced calculators to appraisal the ability acclimated by assorted types of RAM.9

Module and dent characteristics are inherently linked.

Total bore accommodation is a artefact of one chip's accommodation by the bulk of chips. ECC modules accumulate it by 8/9 because they use one bit per byte for absurdity correction. A bore of any accurate admeasurement can accordingly be accumulated either from 32 baby chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR anamnesis bus amplitude per approach is 64 $.25 (72 for ECC memory). Total bore bit amplitude is a artefact of $.25 per dent by bulk of chips. It aswell equals bulk of ranks (rows) assorted by DDR anamnesis bus width. Consequently a bore with greater bulk of chips or application ×8 chips instead of ×4 will accept added ranks.

Example: Variations of 1 GB PC2100 Registered DDR SDRAM bore with ECC Bore admeasurement (GB) Number of chips Chip admeasurement (Mbit) Chip alignment Number of ranks

1 36 256 64M×4 2

1 18 512 64M×8 2

1 18 512 128M×4 1

This archetype compares altered real-world server anamnesis modules with a accepted admeasurement of 1 GB. One should absolutely be accurate affairs 1 GB anamnesis modules, because all these variations can be awash beneath one amount position after advertence whether they are ×4 or ×8, individual or bifold ranked.

There is a accepted acceptance that bulk of bore ranks equals bulk of sides. As aloft abstracts shows, this is not true. One can acquisition 2-side/1-rank or 2-side/4-rank modules. One can even anticipate of a 1-side/2-rank anamnesis bore accepting 16(18) chips on individual ancillary ×8 each, but it's absurd such a bore was anytime produced.

History

Double abstracts amount (DDR) SDRAM specification

From JEDEC Board Ballot JCB-99-70, and adapted by abundant added Board Ballots, formulated beneath the cognizance of Committee JC-42.3 on DRAM Parametrics.

Standard No. 79 Revision Log:

Release 1, June 2000

Release 2, May 2002

Release C, March 2003 – JEDEC Accepted No. 79C.10

"This absolute accepted defines all appropriate aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 abstracts interfaces, including features, functionality, ac and dc parametrics, bales and pin assignments. This ambit will after be broadcast to formally administer to x32 devices, and college body accessories as well."

Organization

PC3200 is DDR SDRAM advised to accomplish at 200 MHz application DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 anamnesis transfers abstracts on both the ascent and falling alarm edges, its able alarm amount is 400 MHz.

1 GB PC3200 non-ECC modules are usually fabricated with sixteen 512 Mbit chips, 8 down anniversary ancillary (512 Mbits × 16 chips) / (8 $.25 (per byte)) = 1,024 MB. The alone chips authoritative up a 1 GB anamnesis bore are usually organized with 64 Mbits and a abstracts amplitude of 8 $.25 for anniversary chip, frequently bidding as 64M×8. Anamnesis bogus in this way is low body RAM and will usually be accordant with any motherboard allegorical PC3200 DDR-400 memory.citation needed

High density RAM

In the ambience of the 1 GB non-ECC PC3200 SDRAM module, there is actual little visually to differentiate low body from top body RAM. Top body DDR RAM modules will, like their low body counterparts, usually be double-sided with eight 512 Mbit chips per side. The aberration is that for anniversary chip, instead of getting organized in a 64M×8 configuration, it is organized with 128 Mbits and a abstracts amplitude of 4 bits, or 128M×4.

High body anamnesis modules are accumulated application chips from assorted manufacturers. These chips appear in both the accustomed 22 × 10 mm (approx.) TSOP2 and abate squarer 12 × 9 mm (approx.) FBGA amalgamation sizes. Top body chips can be articular by the numbers on anniversary chip.

High body RAM accessories were advised to be acclimated in registered anamnesis modules for servers. JEDEC standards do not administer to high-density DDR RAM in desktop implementations.citation needed JEDEC's abstruse documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 getting classified as top density. As such, top body is a about term, which can be acclimated to call anamnesis which is not accurate by a accurate motherboard's anamnesis controller.citation needed

Alternatives

DDR SDRAM

Standard Bus clock

(MHz) Internal rate

(MHz) Prefetch

(min burst) Transfer Rate

(MT/s) Voltage DIMM

pins SO-DIMM

pins MicroDIMM

pins

DDR  100–200  100–200 2n 200–400  2.5/2.6 184 200 172

DDR2 200–533  100–266 4n 400–1066 1.8 240 200 214

DDR3 400–1066 100–266 8n 800–2133 1.5 240 204 214

DDR (DDR1) was abolished by DDR2 SDRAM, which had modifications for college alarm abundance and afresh angled throughput, but operates on the aforementioned assumption as DDR. Competing with DDR2 was Rambus XDR DRAM. DDR2 bedeviled due to amount and abutment factors. DDR2 was in about-face abolished by DDR3 SDRAM which offered college achievement for added bus speeds and new features. DDR3 will acceptable be abolished by DDR4 SDRAM, which was aboriginal produced in 2011 and whose standards are still in alteration (2012) with cogent architectural changes.

DDR's prefetch absorber abyss is 2(bits), while DDR2 uses 4. Although the able alarm ante of DDR2 are college than DDR, the all-embracing achievement was no greater in the aboriginal implementations, primarily due to the top latencies of the aboriginal DDR2 modules. DDR2 started to be able by the end of 2004, as modules with lower latencies became available.11

Memory manufacturers declared that it was abstract to accomplish DDR1 anamnesis with able alteration ante in balance of 400 MHz (i.e. 400MT/s and 200 MHz alien clock) due to centralized acceleration limitations. DDR2 picks up area DDR1 leaves off, utilizing centralized alarm ante agnate to DDR1, but is accessible at able alteration ante of 400 MHz and higher. DDR3 advances continued the adeptness to bottle centralized alarm ante while accouterment college able alteration ante by afresh acceleration the prefetch depth.

RDRAM was a decidedly big-ticket another to DDR SDRAM, and a lot of manufacturers alone its abutment from their chipsets. DDR1 memory's prices essentially added back Q2 2008 while DDR2 prices declined. In January 2009, 1 GB DDR1 was 2–3 times added big-ticket than 1 GB DDR2. Top body DDR RAM will clothing about 10% of PC motherboards on the bazaar while low body will clothing about all motherboards on the PC Desktop market.